View TMPR4955AFG-200_4449205.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tmpr4955af 2002-01-17 1 / 19 tmpr49 55a f -200 tmpr49 55a f -200 (tx4955a) (64- bit risc microprocessor) 1. general description t he tmpr 4955a f is a 64-bit risc (reduced instruction set computer) microprocessor that is a low- cost, low-power microprocessor developed for interactive consumer applications including set-top terminals , lbp(laser beam printer) , and video games. 2. features true 64-bit microprocessor, with tx49 /h2 core. optimized 5-stage pipeline 32-bit system address/data bus single or double-precision floating-point operation 32-bit physical address space and 64-bit virtual address space. 32-bit sysad bus interface with r4000/r4400/r5000 or tx4300 compatible protcol on-chip 32 -kbyte instruction cache and 32 -kbyte data cache. low power consumption 3.3 /1.5 v dual power supply (i/o :3.3v,internal:1.5v ) reduced power mode (halt) data cache prefetching memory management unit contains 48-double entry jtlb, 2-entry instruction tlb, and 4-entry data tlb software compatibility with all mips processors mips i, ii, and iii instruction set architecture (isa) ejtag (enhanced jtag) debug support maximum operating frequency internal:200mhz external:100mhz package : 160-pin qfp the information contained herein is subject to change without notice. toshiba is continually working to improve the quality and the reliability of its products. nevertheless , semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a toshiba product could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent products specifications. also , please keep in mind the precautions and conditions set forth in the toshiba semiconductor reliability handbook the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. toshiba risc processor
tmpr4955af 2002-01-17 2 / 19 tmpr49 55a f -200 3. system configuration 3.1 tmpr49 55a f block diagram tx49/h 2 core tmpr4955 a f integer unit floating-point coprocessor (cp1) system control coprocessor (cp0) cg (pll) synchronizer dsu ( ejtag ) sysad interface gpr mac data path pipeline controller cache controller 32k byte 4-way set instruction cache 32k byte 4-way set data cache write buffer cp1 registers data path cp 0 registers mmu w/ tlb exception unit master clock interrupt /reset jtag interface 32-bit s ys ad bus
tmpr4955af 2002-01-17 3 / 19 tmpr49 55a f -200 3.2 block function q tx49 /h2 core true 64-bit microprocessor 32, 64-bit integer general purpose registers 32 , 64-bit floating point general purpose registers optimized 5-stage pipeline instruction set upward compatible with mips i,mips ii, mips iii isa mac(multiply and accumulate) instructions pref(prefetch) instruction on-chip 32-kbyte instruction cache and 32-kbyte data cache 4-way set associative and lock function support data cache: write-back and write-through support mmu 32-bit physical address space and 64-bit virtual address space 48-double-entry (even/odd) joint tlb 2-entry instruction tlb and 4-entry data tlb ieee754 compatible single and double precision fpu debug support unit (dsu) with ejtag support power management modes ( halt/doze ) q sysad bus i/f bus protocol conversion it converts t mpr 4955 af internal gbus read/write request into outside syad bus protocol. output buffer level selectable q synchronizer the external interrupt it take s contents of interrupt register and bitwise or of external interrupt signal (int(5:0)). q clock generator generates the internal operating clock of the t mpr 4955 af from external crystal oscillator. q debug support unit (dsu) ejtag function support consists of an enhanced jtag (ejtag) module and a debug support unit (dsu). it can be used to provide single-step execution and hardware break-points for debugging processor systems. ejtag utilizes jtag interface and extends the ability to access the inside register contents, host sytem peripherals, and system memory.
tmpr4955af 2002-01-17 4 / 19 tmpr49 55a f -200 4. pin description 4.1 p in out ( 160 -pin qfp) 1 vss 41 vss 81 vccint 121 sysad28 2 bufsel1 42 trst* 82 nmi* 122 sysad29 3 jtdo 43 rdrdy* / (gnd) 83 extrqst* / ( ereq*) 123 vccint 4 jtdi 44 wrrdy* / (eok*) 84 reset* 124 vss 5 jtck 45 validin* / ( evalid*) 85 coldreset* 125 sysad30 6 jtms 46 validout* / ( pvalid*) 86 vccio 126 vccio 7 vccio 47 release* / ( pmaster*) 87 endian 127 vss 8 vss 48 vccio 88 vccio 128 sysad31 9 sysad4 49 pllreset* 89 vss 129 sysadc2 / (gnd) 10 sysad5 50 vccint 90 sysad16 130 vccint 11 vccint 51 tintdis 91 vccint 131 vss 12 vss 52 vss 92 vss 132 sysadc3 / (gnd) 13 sysad6 53 syscmd0 93 sysad17 133 vccio 14 vccio 54 syscmd1 94 sysad18 134 vss 15 vss 55 syscmd2 95 vccio 135 sysadc0 / (gnd) 16 sysad7 56 syscmd3 96 vss 136 vccint 17 sysad8 57 syscmd4 97 sysad19 137 vss 18 vccint 58 syscmd5 / (gnd) 98 vccint 138 sysadc1 / (gnd) 19 vss 59 vccio 99 vss 139 sysad0 20 sysad9 60 vss 100 sysad20 140 vccio 21 vccio 61 syscmd6 / (gnd) 101 sysad21 141 vss 22 vss 62 syscmd7 / (gnd) 102 vccio 142 sysad1 23 sysad10 63 syscmd8 / (gnd) 103 vss 143 sysad2 24 sysad11 64 syscmdp / (gnd) 104 sysad22 144 vccint 25 vccint 65 vccint 105 vccint 145 vss 26 vss 66 vss 106 vss 146 sysad3 27 sysad12 67 vccio 107 sysad23 147 pcst8 28 vccio 68 halt/doze 108 sysad24 148 pcst7 29 vss 69 int0* 109 vccio 149 pcst6 30 sysad13 70 int1* 110 vss 150 pcst5 31 sysad14 71 int2* 111 sysad25 151 pcst4 32 vccint 72 int3* 112 vccint 152 vccio 33 vss 73 int4* 113 vss 153 vss 34 sysad15 74 int5* 114 sysad26 154 vccio 35 bufsel0 75 vccio 115 sysad27 155 vsspll 36 pcst3 76 vss 116 vccio 156 pllcap 37 pcst2 77 tpc3 117 mode43* 157 vccpll 38 pcst1 78 tpc2 118 divmode1 158 vss 39 pcst0 79 tpc1 119 divmode0 159 masterclock 40 vccio 80 dclk 120 vss 160 vccio note1: ? * ? means the signal is the low-active. note2: mode43* sysad bus protocol select. 0 : tx4300 protocol 1 : r5000 protocol note3: at tx4300 protocol mode preq* signal i s not support.
tmpr4955af 2002-01-17 5 / 19 tmpr49 55a f -200 4.2 pin function the following is a list of interface, interrupt, and miscellaneous pins available on the tmpr4955 a f. system interface (when mode43* = 1) pin name i / o function sysad( 31 :0) i / o system address / data bus a 32-bit address and data bus for communication between the processor and an external agent. syscmd( 8 :0) i / o system command / data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. sysadc(3:0) i / o system command/data check bus a 4-bit bus containing parity check bits for the sysad bus during data cycles. syscmdp i / o reserved for system command/data identifier bus parity for the tmpr4955af this signal is unused on input and zero on output. valid in * i valid input the external agent asserts valid in * when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. valid out * o valid output the processor asserts valid out * when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. e xt rq st * i external request an external agent asserts extrqst* to request use of the system interface . re lease * o release interface signals that the system interface needs to submit an external request. wrrdy * i write ready signals that an external agent can now accept a processor write request. rdrdy * i read ready signals that an external agent can now accept a processor read request.
tmpr4955af 2002-01-17 6 / 19 tmpr49 55a f -200 system interface (when mode43* = 0) pin name i / o function sysad( 31 :0) i / o system address / data bus a 32-bit address and data bus for communication between the processor and an external agent. syscmd( 4 :0) i / o system command / data identifier bus a 9-bit bus for command and data identifier transmission between the processor and an external agent. syscmd( 8 : 5 ) / gnd o reserved always output low level signal. sysadc(3:0) / gnd o reserved always output low level signal. syscmdp / gnd o reserved always output low level signal. valid in * / evalid* i valid input the external agent asserts ev alid* when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. valid out * / pvalid* o valid output the processor asserts p valid* when it is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. e xt rq st * / ereq* i external request an external agent asserts er e q* to request use of the system interface . release * / pmaster* o processor master show that the tmpr4955af is the system bus master. wrrdy * / eok* i external ok signals that an external agent can now accept a processor write request. rdrdy * / gnd i reserved always input low level signal. this signal has the internal pull-down registor.
tmpr4955af 2002-01-17 7 / 19 tmpr49 55a f -200 clock / control interface pin name i / o function masterclock i master clock master clock input that establishes the processor operating frequency. divmode(1:0) i set the operational frequency of the system interface divmode ( 1:0 ) masterclock p cl ock 0 0 50.0 mhz 200 mhz (1:4) 0 1 80.0 mhz 200 mhz (1:2.5) 10 100.0 mhz 200 mhz (1:2) 11 66.7 mhz 200 mhz (1:3) t int d is i timer-interrupt disable input 0 enable timer-interrupt (can not use int5*) 1 disable timer-interrupt halt /doze o halt/doze mode output this signal indicates that the tmpr4955af is in the halt or doze mode when this signal is ? h ? . pllreset* i pll reset input a signal to halt the pll oscillation of the tmpr4955af built-in clock generator. 0 pll is halt (no oscillation ) 1 pll is enabled. e ndian i endianess input indicates the initial setting of the endian during a reset. 0 little endian 1 big endian interrupt interface pin name i / o function int(5:0)* i interrupt five general processor interrupts, bit-wise ored with bits 5:0 of the interrupt register and visible as bits 15:10 of the cause register. nmi* i non- maskable interrupt non- maskable interrupt, ored with bit 6 of the interrupt register.
tmpr4955af 2002-01-17 8 / 19 tmpr49 55a f -200 jtag interface pin name i / o function jtdi i jtag data in put / debug interrupt input run-time mode : input serial data to data/instruction register of jtag. real-time mode : interrupt line to change the debug unit state from real time mode to run-time mode. jtck i jtag clock input the processor receives a serial clock on jtck. on the rising edge of jtck, both jtdi and jtms are sampled. jtdo /tpc(0) o jtag data out put / pc trace output run-time mode : output serial data from data/instruction register of jtag. real-time mode : output non-sequential program. jtms i jtag command jtag command signal, indicating the incoming serial data is command data. dclk o debug clock a clock output for a real-time debug system. the timing of a serial monitor bus and pc trace interface signal are all defined by this debug clock dclk. the operation clock of the tmpr4955af is divided by 3 at the time of a serial monitor bus operation. pcst (8:0) o pc trace status output pc trace status information and the mode of the serial monitor bus. tpc (3:1) o pc trace output output a non-sequential program counter at dclk. trst* i test reset input a reset input for a real-time debug system. when trst* is asserted, the debug support unit (dsu) is initialized.
tmpr4955af 2002-01-17 9 / 19 tmpr49 55a f -200 initialization interface pin name i / o function reset* i soft (warm) reset this signal must be asserted synchronously with masterclock for a soft reset. coldreset* i cold reset this signal indicates to the processor that the +3.3v (i/o) and +1.5v(internal) power supply is stable and the processor should initiate a cold reset sequence, resetting the pll. mode43* i mode43* sysad bus protocol select. 0 tx4300 protocol 1 r5000 protocol bufsel(1:0) i output buffer level select bufsel( 1:0 ) level 0 0 50% (4ma buffer) 0 1 reserved 10 150% (12ma buffer) 11 100% (8ma buffer) pllcap i pll connect to capacitor non connection. others pin name i / o function vccp ll i quiet v cc for pll quiet v cc for the internal phase locked loop. (1.5v) vssp ll i quiet v ss for pll quiet v ss for the internal phase locked loop. vccio i vcc power supply pin for io.( 3.3v ) vccint i vcc power supply pin for internal.(1.5v) vss i vss ground pin
tmpr4955af 2002-01-17 10 / 19 tmpr49 55a f -200 5. electrical characteristics note: ? be careful of static ? , please see ? from incoming to shipping ? of general safety precautions and usage considerations. 5.1 absolute maximum ratings tmpr495 5a f- 200 v ss = 0 v (gnd) parameter symbol ratings unit supply voltage ( for i/o) vcciomax -0.5 to 3.9 v supply voltage ( for internal ) vccintmax -0.5 to 3.0 v input voltage (*1) (*2) v in -0.5 to v cc + 0.3 v storage temperature t stg -65 to +150 c note ) if lsi is used above the maximum ratings, permanent destruction of lsi can result. in addition, it is desirable to use lsi for normal operation under the recommended condition. if these conditions are exceeded, reliability of lsi may be adversely affected. (*1) vin min . = -1.5v for pulse width less than 10 ns. (*2) keep (vccio + 0.3v) less than vcciomax 5.2 recommended operating conditions tmpr4955 a f- 200 v ss = 0 v (gnd) parameter symbol conditions min. max. unit supply voltage ( for i/o ) vccio 3. 1 3. 5 v supply voltage ( for internal ) vccint 1.4 1.6 v operating case temperature t c 0 + 70 c note : the recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac and dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to.
tmpr4955af 2002-01-17 11 / 19 tmpr49 55a f -200 5.3 dc characteristics tmpr4955 a f- 200 t c = 0 c to 70 c, vccint = 1.5v 0.1v, vccio = 3.3 v 0.2v parameter sym bol conditions min. typ . max. units output high voltage v oh vccio = 3.3v,vss=0v i oh = -4 ma 2.4 v output low voltage v ol vccio = 3.3v,vss=0v i ol = 4 ma 0.4 v input high voltage (*2) v ih 2.0 vccio+ 0.3 v input low voltage (*1,2) v il -0.5 (*1) 0.8 v operating current 1 (normal operation) i cc int vccio = 3. 3 v, vccint = 1.5v, masterclock=100mhz, pclock = 200mhz 350 550 m a operating current 2 (halt mode) i cc int vccio = 3. 3 v, vccint = 1.5v, masterclock=100mhz, pclock = 0mhz 150 m a operating current 3 ( masterclock stopped) i cc int vccio = 3. 3 v, vccint = 1.5v, masterclock=0mhz, pclock = 0mhz 50 m a operating current i cc io vccio = 3. 3 v, vccint = 1.5 v, masterclock=100mhz, pclock = 200mhz load = 25pf 50 60 m a input leakage i li except (*3)port 10 m a pull-up (*3) rin u 30 50 100 kohm pull- down (* 4 ) rin d 30 50 1 0 0 kohm output leakage i lo 20 m a input capacitance c in 10 pf output capacitance c out 10 pf (*1) v il min. = -1.5v for pulse width less than 10 ns. (*2) except for masterclock input (*3) applies to int ( 5 : 0 )*, nmi*, reset*, jtms, jtck, jtdi, tpc1 inputs with pull-up resistor (* 4 ) applies to trst* ,rdrdy*,tpc3,tpc2 inputs with pull-down resistor
tmpr4955af 2002-01-17 12 / 19 tmpr49 55a f -200 5.4 ac characteristics 5.4.1 clock timing tmpr4955 a f- 200 t c = 0 c to 70 c, vccint = 1.5v 0.1v , vccio = 3.3 v 0.2v parameter symbol conditions min. max. units masterclock high t mch transition 5 ns 3.0 ns masterclock low t mcl transition 5 ns 3.0 ns masterclock frequency (*1) f mck 20 100.0 mhz internal operation frequency f pck 50 200 mhz masterclock period t mcp 1 0 50 ns masterclock rise time t mcr 2.0 ns masterclock fall time t mcf 2.0 ns (*1) operation of tmpr495 a f is only guaranteed with the phase lock loop enabled. (*2) all output timings assume a 25 pf capacitive load. output timings should be derated where appropriate. 5.4.2 system interface tmpr4955 a f- 200 t c = 0 c to 70 c, vccint = 1.5v 0.1v , vccio = 3.3 v 0.2v, bufsel=100% parameter symbol min. max. units data output ( *1,2,3 ) t do 1.0 6.5 ns data setup ( *3 ) t ds 3 .5 ns data hold ( *3 ) t dh 1.0 ns (*1) timings are measured from 1.5v of the sclock to 1.5v of signal. (*2) capacitive load for all output timings is 25 pf. (*3) data output, data setup and data hold apply to all logic signals driven out of or driven into the tmpr4955 a f on the system interface. clocks are specified separately.
tmpr4955af 2002-01-17 13 / 19 tmpr49 55a f -200 5.5 timing diagrams 5.5.1 clock timing t mch t mcl t mcp masterclock 0.8 * vccio 0.2 * vcc io t mcr t mcf
tmpr4955af 2002-01-17 14 / 19 tmpr49 55a f -200 5.5. 2 pclock to sclock divisor of 2 cycle masterclock pclock (internal signal) sclock (internal signal) sysad driven sysad received 4 3 2 1 d d d d t do d d d d t dh t ds
tmpr4955af 2002-01-17 15 / 19 tmpr49 55a f -200 5.5. 3 system interface timing valid input valid output valid input masterclock sclock (internal signal) sysad syscmd sysadc syscmdp valid out *, release * valid in *, e xtrqst *, wr r dy*, rdrdy*, int(5:0)*,nmi* t dh t ds t do t do t do t dh t ds
tmpr4955af 2002-01-17 16 / 19 tmpr49 55a f -200 5.5. 4 cold reset timing 5.5. 5 warm reset timing masterclock divmode(1:0) reset* coldreset* more than 64000 masterclock t ds t dh masterclock reset* coldreset* more than 16 masterclock cycles t ds t dh t ds more than 16 masterclock cycles t dh t ds
tmpr4955af 2002-01-17 17 / 19 tmpr49 55a f -200 6. package dimension qfp 160-p-2 828-0. 65a unit : mm
tmpr4955af 2002-01-17 18 / 19 tmpr49 55a f -200 7 . pll passive components the phase locked loop circuit requires several passive components for proper operation, which are connected to vccpll, and vsspll, as illustrated in figure 1. in addition, the capacitors for pllcap (cp) can be connected to either vccpll. note that c2 and the cp capacitors are only incorporated into the qfp package as surface-mounted chip capacitors. figure 1 pll recommended circuit reference values : r = 5 w (*1) c1 = 1 nf (*1) c2 = 82 nf (*1) c3 = 10uf (*1) vccint = 1.5 v 0.1 v note *1 : change to the suitable value on each board the inductors (l) can be used as alternatives to the resistors (r) to filter the power supply. it is essential to isolate the analog power and ground for the pll circuit (vccpll/vsspll) from the regular power and ground (vccint/vss). tx4955a vccint vccpll pllcap (reserved) vsspll vss c1 c2 c3 r l c1, c2, c3, r and l are board components which should be placed as close as possible to the processor. r l
tmpr4955af 2002-01-17 19 / 19 tmpr49 55a f -200 8 . differences between the tmpr4955f and the tmpr4955af product name tmpr4955f tmpr4955af power supply: core (incl. pll) i/o 2.5v 3.3 v 1.5v 3.3 v pin assignment (no.2) and (no.35) vccio vccio bufsel1 bufsel0 i/o buffer drive (ratio) 1.0 selectable from 0.5, 1.0 and 1.5 note: bufsel (1:0) = 11 10 01 00 output drive ratio = 100% 150% reserved 50% influenced signals i/o 1 sysad(31:0) i/o syscmd(8:0) i/o sysadc(3:0) i/o syscmdp i/o validout* o release* o haltdoze o 9 . history 2000-9-29 2000-10-12 page-9 others of pin function vccpll 2.5v -> 1.5v 2000-11-17 ac and dc specification pll passive components 2002-1- 17 deleated 167mhz spec.

▲Up To Search▲

Price & Availability of TMPR4955AFG-200

	To Download TMPR4955AFG-200 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .